The candidate will be expected to work with a team of engineers
Write synthesizable designs (RTL) in Verilog/VHDL to test various domains and features of RTL Compiler. Run Physical Synthesis and correlate the physical synthesis results with backend tools.
Debugging the correlation and QoR gaps. Write programs and scripts to help automate tests. Contribute to make the solution better by working with RnD teams.
Industry TypeIT-Software, Software Services
Functional AreaIT Software – Embedded, EDA, VLSI, ASIC, Chip Design
Employment TypeFull Time, Permanent
Role CategoryProgramming & Design
UG :Any Graduate in Any Specialization
PG :Post Graduation Not Required
Salary : according to interview
VHDLBackendInternVerilogDebuggingManager Technologyproduct validationRTLTesting