Develop complex FPGA logic architecture, code, simulation, and Verification
Hands on bench testing of new designs for compliance to design specifications.
Complete documentation throughout design and development cycle from theory of operation to test specifications
Responsible for communication and coordination with Software, Hardware, System Engineering and Validation, teams throughout the design and development cycle
Coordinate with technical team members design reviews, feature specifications, etc.
Attend meetings, report progress, and take technical leadership to troubleshoot and fix defects.
Provide guidance and mentoring for junior engineers hired into the team who may be tasked to perform some of the above duties.
Help investigate and collect information to resolve process or design issues found on a current design or in previous designs.
Assumes other duties as assigned
High speed FPGA/IP block logic design for Packet Networking equipment.
Design of Layer 2 or Layer 3 IP blocks for Ethernet/IP protocols with packet parsing, switching, routing, traffic management, scheduling, shaping, admission control functions in FPGAs or ASICs with 1Gb Ethernet to 400Gb Ethernet/IP designs.
Knowledge with industry standards such as IEEE 802.3 standards for 1/10G , 100G Ethernet PCS and MAC layers , OAM , SAT , MEF standards, ITU-T standards, relevant RFCs such as Pseudowires, Ethernet metering etc. 5G Radio fronthaul standards such as RoE(Radio over Ethernet), Open RAN, CPRI/eCPRI standards.
FPGA/ASIC front end design using synthesis and simulations tools with System Verilog and/or VHDL.
Worked as design lead for full FPGA/ASIC or IP blocks.
Timing closure for FPGA or ASICs. Fully aware for timing constraints and methodologies.
Keen to develop FPGAs/ASIC blocks with high quality following rigorous quality checklists and methodologies.
Experienced with PERL/Python scripting.
Block/IP level verification of the same.
Validation of such FPGA/ASIC in System towards final deliverables.
Strong knowledge of using design tools for analysis, development, testing, and debug.
Knowledge and experience designing with Altera/Intel and Xilinx FPGAs with Quartus or Vivado tools.
Use of standard bench level test equipment such as oscilloscopes, logic analyzers, and other supporting equipment.
Ability to resolve complex issues that may require design trade-offs.
Excellent verbal and written communication skills.
DESIRED CHARACTERISTICSSelf-starter with positive attitude
Team orientation, organized, and capable of independent work
Acumen for problem solving. Ability to lead in an environment of change flexibility, creativity and patience
Ability to learn and grasp technical concepts related to products being developed
Able to work effectively and communicate at all levels within the Ciena workforce
EDUCATION / EXPERIENCEB.E/BTech in Electronics Engineering and/or M.Tech preferred
Minimum 8+ years experience doing FPGA/ASIC design from requirements, using FPGA development tools with Verilog and/or VHDL.
Salary: Not Disclosed by Recruiter
Functional Area:IT Software – Embedded, EDA, VLSI, ASIC, Chip Design
Role Category:Programming & Design
Role:Team Lead/Technical Lead
Employment Type:Full Time, Permanent
front endpythonVHDLSimulationFPGAtestingVerilogEthernetnetworkingPerlSystem verilogMPLS
Desired Candidate Profile
Please refer to the Job description above
UG:B.Tech/B.E. – Computers
PG:M.Tech – Computers
Doctorate:Doctorate Not Required
Ciena India Private Ltd.
Ciena® Corporation, the network specialist, expanded its global presence with the launch of a R&D centre located in Gurgaon, India. The 95,000 square foot facility is Ciena’s first core research and development centre outside of North America, and is expected to employ more than 300 product development engineers within the next three years.
Ciena’s Gurgaon R&D Centre will focus on technologies such as Storage Extension and Optical Transport, including ultra long-haul, long-haul, regional and metropolitan applications, as well as Multiservice Switching, Broadband Access and Network Management. The Gurgaon Centre will supplement and work collaboratively with Ciena’s existing research and development organization in North America.